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[Other resource] 异步FIFO存储器的控制设计

Description: 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
Platform: | Size: 6655 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[VHDL-FPGA-Verilog] c22_FIFO

Description: 精通verilog HDL语言编程源码之8——异步FIFO设计-Proficient in language programming verilog HDL source of 8- Asynchronous FIFO Design
Platform: | Size: 2048 | Author: 李平 | Hits:

[OS Develop] fifo

Description: 基于verilog的异步fifo设计，仿真效果良好-asynchronous fifo based on zhe verilog language
Platform: | Size: 5120 | Author: 颜良飞 | Hits:

[VHDL-FPGA-Verilog] afifo

Description: verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
Platform: | Size: 1024 | Author: 查乐 | Hits:

[VHDL-FPGA-Verilog] ad_da_ctr

Description: 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simulation results are basically correct.
Platform: | Size: 2299904 | Author: ych | Hits:

[VHDL-FPGA-Verilog] AsynFIFO

Description: Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
Platform: | Size: 32768 | Author: 郑宇龙 | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design, which write clock 100MHz, read clock is 5MHz, the depth of the RAM 256. When the rising edge of write clock pulse when writing the signal is valid, then write an eight-bit data to RAM when the rising edge of read clock pulse, the judge read the signal is valid, from eight bits of data in RAM to a read out. When RAM is full of data to generate a full mark, can not go down RAM write data when the RAM data read empty an empty sign, can not read data from RAM.
Platform: | Size: 333824 | Author: 肖波 | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
Platform: | Size: 12288 | Author: 范先龙 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
Platform: | Size: 3072 | Author: zx | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: Verilog HDL语言编写异步FIFO-Verilog HDL language, asynchronous FIFO
Platform: | Size: 3072 | Author: 赵鑫 | Hits:

[VHDL-FPGA-Verilog] FIFO-and-CAM

Description: verilog code for gray counter,synchronous and asynchronous fifo
Platform: | Size: 25600 | Author: Abhijeet | Hits:

[Other] fifo

Description: 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
Platform: | Size: 175104 | Author: zhaoyibin | Hits:

[VHDL-FPGA-Verilog] asynchronous-FIFO-verilog

Description: FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write address lines, very simple to use
Platform: | Size: 14336 | Author: chenkun | Hits:

[VHDL-FPGA-Verilog] async_fifo-and-verilog

Description: 异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed description of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
Platform: | Size: 12288 | Author: 雨茗 | Hits:

[Other] fifo

Description: 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
Platform: | Size: 1024 | Author: 曹伟 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步FIFO的verilog实现，可以参考一下-Verilog asynchronous FIFO implementation, you can refer to
Platform: | Size: 51200 | Author: kobe | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
Platform: | Size: 2048 | Author: 大黄黄黄 | Hits:

[VHDL-FPGA-Verilog] verilog实例 [43项]

Description: 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
Platform: | Size: 190464 | Author: hayto | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)
Platform: | Size: 2048 | Author: wt2110 | Hits:
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